ZoTech IP for FPGA

All IP are written in C++ and synthesized using Xilinx’s Vivado High Level Synthesis tool. The current version used for development and verification is 2016.4. The resource utilization and timing results shown in the tables are taken after the completion of place and route by the Vivado tools.


Communication IP

Viterbi Decoder

ZoTech’s Viterbi Decoder is tuned for wireless applications and able to process data at up to 720 Mbits per second, running at 360 MHz, 2 bits per cycle.Our Viterbi Decoder is bit-accurate with Matlab’s vitdec() function.

View the Product Specification (pdf)

Viterbi Decoder Resource Utilization

1 output bit per cycle1020460476570464 MHz
2 output bits per cycle369321477298980361 Mhz

* 1 output bit/cycle: soft bit-width = 5, traceback length = 48
* 2 output bits/cycle: soft bit-width = 5, traceback length = 128

LDPC Decoder

ZoTech’s LDPC (Low Density Parity Check) Decoder can be synthesized with different levels of parallelism, providing an output rate of up to 640 Mbits per second, with 5 iterations.

View the Product Specification (pdf)

LDPC Decoder Resource Utilization

Min Size178392888164120410 MHz
Max Throughput139598471298614360364 Mhz

Since a LDPC Decoder’s performance depends on several parameters, the actual throughput will vary for different communication standards.

For further information, please contact us by email


ZoTech offers free IP that can be downloaded and used as-is. These IP are examples of high speed design written in C++ for FPGA using Vivado HLS.


Direct Digital Synthesizer (DDS)

ZoTech’s DDS (Direct Digital Synthesizer) is a Sin/Cos waveform generator that can be used for creating arbitrary waveforms for communication, medical, audio and other applications. Our DDS IP consists of a parameterizable phase accumulator, sin/cos look-up table and optional Taylor Approximation (from zero up to three terms). The IP runs at speeds of up to 500 Msps (Megasamples per second) on the slowest grade Kintex Ultrascale FPGAs.

Direct Digital Synthesizer Resource Utilization

Look-up Table Only (phase: 32 bits, data: 12 bits)5519223411502 MHz
Taylor, 1 term (phase: 32 bits, data width: 18 bits)133392830101513 MHz
Taylor, 2 terms (phase: 32 bits, data: 24 bits)2848441947161513 MHz
Taylor, 3 terms (phase: 32 bits, data: 32 bits)159241998256931493 MHz

The IP will be available for download shortly. Meanwhile, please send any requests to



Many FPGA designs require division to be performed in a context where 1 output per clock-cycle is not necessary. One example is for block data processing, where division is done once initially to calculate a reciprocal value that is then used as an input for multiplication for the entire block. Zotech offers a small footprint, high-frequency divider IP that is often perfect for these types of applications. Our Divider offers the benefits of low-latency and dramatically reduced FPGA footprint at the expense of a small decrease in throughput.

Divider Resource Utilization

High-Frequency Divider: (num: 18 bits, den: 18 bits)4119324200595 MHz
Low-Frequency Divider: (num: 18 bits, den: 18 bits)201066200251 MHz
High-Frequency Divider: (num: 48 bits, den: 48 bits)8347165100595 MHz
Low-Frequency Divider: (num: 48 bits, den: 48 bits)3922615300207 MHz

The IP will be available for download shortly. Meanwhile, please send any requests to