Design Service

  • High level synthesis (C/C++/SystemC) for FPGA
  • Software/Hardware co-design
  • OpenCL

Tool Expertise

  • Vivado HLS
  • SDAccel (OpenCL compiler for FPGA)
  • SDSoC
  • Matlab, SysGen







RSA 2048 sign and verification running on AWS is a new addition to our product portfolio. To a big extent, this is an experiment and we are still trying to understand the customer requirements and use cases. We are happy to work together with the potential RSA 2048 users, helping you to run the existing application and/or making necessary changes. 
Please, don’t hesitate to contact us via support@zotechgroup.com






xfOpenCv library is Xilinx implementation of OpenCV for SDSoC platform. ZoTech added a demo showing how it can be run on AWS using OpenCL compiled by SDAccel. The demo is currently available from ZoTech’s github page.

Design Service Expertise

Starting with the customer algorithm, ZoTech engineers convert customer algorithms into FPGA implementations that maximize use of the available resources.


The core of many DSP algorithms are filters and transforms. We implement both IIR and FIR filters such that all the available symmetries are efficiently used and there are neither empty cycles nor unnecessary data calculation.






Since a lot of algorithms require linear algebra functions such matrix inversion, matrix multiplication or eigenvalue calculation, we implement these algorithms using floating and fix point representation, fighting the data dependency with the massive parallelism generated by processing many matrices or sub-matrices in parallel.





Wireless applications are based on DSP algorithms, but they also have specific functions such as error correction, modulation, interleaving etc. ZoTech implements these functions for multichannel applications, parametrizable and adopted for different standards.






Very few applications nowadays can run without some code running on the microprocessor. ZoTech engineers can implement systems that include both hardware and software in programmable SoC devices using any flow available from Xilinx: IPIntergrator and SDK, SDSoC and SDAccel.






FPGAs are efficient for the implementation of the Image processing algorithms. ZoTech’s implementation can be based on hardware-optimized OpenCV functions, e.g. xfOpenCv or fully custom algorithms e.g. for feature extraction, image (pre)processing for neural networks or encoding.






As FPGAs are getting increasingly suitable for automotive applications, new algorithms based on machine learning are being implemented by ZoTech’s customers, and ZoTech’s engineers are making them FPGA-optimized in order to meet customer’s stringent power and performance goals.